منابع مشابه
SAR ADC in 65 nm CMOS
This paper presents a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design for sensor applications. An energy-saving switching technique is proposed to achieve ultra low power consumption. The measured Signal-to-Noise-and-Distortion Ratio (SNDR) of the ADC is 58.4 dB at 2 MS/s with an ultra-low power consumption of only 6.6 μW from a 0.8V supply, resulting in a Figure-...
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A 7-bit, 2.6 GS/s time-interleaved analogue-to-digital converter (ADC) for 60 GHz applications is designed and fabricated in 65 nm CMOS. The proposed subranging ADC architecture with time-shifting track-and-hold and two-phase amplification and encoding significantly enhances the speed of individual ADCs and reduces the number of interleaved channels to only four. At 2.6 GS/s sampling rate with ...
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+ Katholieke Universiteit Leuven, Kasteelpark Arenberg 10, B-3001 Heverlee, [email protected] . Abstract The design plan and measurement results of a very high-speed 6 bit CMOS Flash ADC converter are presented. The very high acquisition speed is obtained by improved comparator design. At these high frequencies power-efficient error correction logic is necessary. Measurements show th...
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Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes have an adverse effect on area and power consumption and, more seriously, do not scale easily to low-voltage processes. We describe a digital technique which removes the accuracy constraints from the comparators. With no analog matching requirements, the comparators c...
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ژورنال
عنوان ژورنال: Science China Information Sciences
سال: 2014
ISSN: 1674-733X,1869-1919
DOI: 10.1007/s11432-014-5101-0